Espressif Systems /ESP32-P4 /SPI3 /SPI_MISC

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Interpret as SPI_MISC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_CS0_DIS)SPI_CS0_DIS 0 (SPI_CS1_DIS)SPI_CS1_DIS 0 (SPI_CS2_DIS)SPI_CS2_DIS 0 (SPI_CK_DIS)SPI_CK_DIS 0SPI_MASTER_CS_POL 0 (SPI_SLAVE_CS_POL)SPI_SLAVE_CS_POL 0 (SPI_CK_IDLE_EDGE)SPI_CK_IDLE_EDGE 0 (SPI_CS_KEEP_ACTIVE)SPI_CS_KEEP_ACTIVE 0 (SPI_QUAD_DIN_PIN_SWAP)SPI_QUAD_DIN_PIN_SWAP

Description

SPI misc register

Fields

SPI_CS0_DIS

SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.

SPI_CS1_DIS

SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.

SPI_CS2_DIS

SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.

SPI_CK_DIS

1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.

SPI_MASTER_CS_POL

In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.

SPI_SLAVE_CS_POL

spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.

SPI_CK_IDLE_EDGE

1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.

SPI_CS_KEEP_ACTIVE

spi cs line keep low when the bit is set. Can be configured in CONF state.

SPI_QUAD_DIN_PIN_SWAP

1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.

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